Commentary

And then bear in mind that the father of telephony is telling all design engineers a cautionary tale: Documentation. Documentation. Documentation.

Half the price, a 1GHz processor, 2GB of integrated storage and some 'interesting' plug-in capes. All for $45. Let the wild Linux-Making begin.

With both now more dependent on foundry business for their finFET (trigate) and FDSOI offerings, DATE was a chance to push their innovations in low power.

Docea Power extends power and thermal analysis tools to address complexity and sub-dividing responsibilities among architects.

Don't underestimate the influence of metallic nanotubes and tube alignment, say Stanford researchers.

Leading vendors and users spoke of the challenges in developing today's SoCs when faced with a plethora of prototyping techniques - and the challenges that remain.

As DVCon begins, we interview Cadence's Qi Wang, who has led its efforts to converge the Common Power Format with its rival as the IEEE1801 standard is revamped.

Keynoter Lisa Su spun a whimsical idea to serious intent as AMD looks to promote its model for heterogeneous architectures

You can now get a complete system-level flow, but bundling 'free' ESL with RTL tools slows the methodology shift, says the leading design analyst. Meanwhile, Cadence moves into the number two vendor slot, but the battle rages on.

Ambipolar FETs, which can be n or p-type dependent on a control gate, could offer a new way to design circuits at 20nm and below.