EDA

Struggling with how to make your debug triage process more efficient? A new checklist could help focus your efforts.

If current market trends persist, shortages in wafers are likely to follow, hurting the ability of some companies to ship silicon and boost the prices for those who can.

Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.

Better integration of EM modeling and analysis tools with Synopsys' Custom Compiler should enable tighter design margins

As geometries have shrunk, layout-dependent effects in CMOS have become ever more problematic. They are not just popping up in performance but reliability and aging effects as one IEDM presentation showed.

IC Manage is expanding its work on big data in EDA with the creation of a labs program that aims to work with clients on novel ideas for analyzing the gigabytes of output from chip-design tools.

ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262

Two leading European research institutes presented their work on the feasibility and cost-effectiveness of monolithic 3D integration at this year's IEDM.

UPF power state tables have become unwieldy due to rapid growth in LP design. The new construct, 'add_power_state' enables better verification flows.

The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.