EDA

ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262

Two leading European research institutes presented their work on the feasibility and cost-effectiveness of monolithic 3D integration at this year's IEDM.

UPF power state tables have become unwieldy due to rapid growth in LP design. The new construct, 'add_power_state' enables better verification flows.

The RISC-V workshop in California at the end of November 2017 provided the opportunity for Western Digital to commit its own work on processors for internal use to the open-source architecture and for the ecosystem of off-the-shelf cores and tools to expand.

X-Fab has added a process module to its wide voltage- and temperature-range 180nm mixed-signal process that supports a set of transistors with lower 1/f flicker noise.

Minima Processor is working on the first processor cores that will be customized to use its timing-control technology to push supply voltages into the near-threshold zone.

Solido acquisition will also add further machine learning expertise to Mentor's capabilities.

Maxim has used its own mismatch-based PUF technology to support a new line of low-cost security devices.

Microsemi has set up an ecosystem program around the RISC-V soft cores the company has designed for its FPGAs.

Intel and GlobalFoundries will talk about their post-14nm finFET-based processes at December's IEDM.