CPU architecture


January 23, 2018

Codasip updates processor-architecture tools

Codasip has launched the seventh generation of its Studio software for processor design and tuning, aiming to take advantage of the interest in RISC-V as a core instruction set for customized processors.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , ,   |  Organizations:
November 5, 2013

Synopsys aims at fast real-time apps with ARC HS family

Synopsys has launched the ARC HS family of configurable-processor cores, using superpipelining to target high-performance embedded applications.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations:

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