Samsung certifies Synopsys tools, IP at 14nm

By Luke Collins |  No Comments  |  Posted: June 2, 2014
Topics/Categories: Conferences, Design to Silicon, Blog - IP  |  Tags: ,  | Organizations: , ,

Samsung has certified Synopsys’ tools and IP for use on its emerging 14nm processes.

Speaking on the first day of DAC, Kelvin Low, senior director of foundry marketing at Samsung, said the company has already produced more than 30 test chips and “more than five” production designs at 14nm.

Samsung has already released its 14LPE process and is working on a performance-enhanced 14LPP version, for which it is already offering PDKs.

Samsung says the process will be 14% faster than a 28nm process at the same leakage, use 81% of the power at the same speed, and will take 55% of the area. Low also claimed that the Samsung process was more than 10% smaller than competing finFET processes, due to using an aggressive gate pitch and a highly compactable memory layout.

“I expect to see production uptake at the end of this year,” said Low.

Kelvin Low of Samsung

Image Kelvin Low of Samsung

After three years of working closely with Samsung and ARM to enable finFET based design, Synopsys’ Galaxy Design Platform and DesignWare IP have now been proven on multiple SoC designs using the 14nm finFET process, the company said.

Synopsys has been working to minimise the impact of the shift to the finFET topology on logic designers by enhancing its flow. In practice, this means doing things like ensuring that IC Compiler understands the need for finFETs to be laid out on a grid, can check aspects of the design such as pin accessibility, and handle via clustering where necessary.

Rob Aitken, ARM fellow, who has been working with Samsung to co-optimise ARM’s cores and Samsung’s finFET process, said that in terms of design, finFET processes  are not really that different. There are fewer threshold voltage options, a different variability profile and better leakage performance.

“You have to be aware of technology issues such as the higher current drive of finFETs and the increased resistivity of the interconnect, and so you have to pay attention to the power grid and IR drop,” he added.

Designers also need to be aware of the impact of double patterning on place and route strategies.

“Most of this stuff is not rocket science and can be handled with current flows and tools,” Aitken added.

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