Flash Memory Summit: Memblaze demos Toshiba ULL NVM technology
The Chinese memory module specialist will preview the 2020 launch of its new solution based on the ultra low latency XL-Flash technology from Toshiba.
Blog Topics
Accellera sets up public code repository
Accellera has set up a public repository for the source code and other supplemental material needed for its standards.
A repeatable methodology for modern reset domain crossing issues
Reset domain crossing is another area where rising SoC complexity and IP reuse is causing an increase in reliability and safety challenges.
Arm opts for more flexibility in licensing
Arm has introduced a licensing model that makes it easier to try out cores during a design before committing to production.
C++ signoff made real
Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.
Coventor updates process simulation tool
Coventor has updated its SEMulator virtual-fab tool and added the ability to tune process windows based on simulation results.
The road to ES Design West: Design Pavilion
ES Design West aims to help integrate the supply chain but also has plenty of engineering content aimed at low power, security, embedded and more.
DVCon US and India chapters issue calls for submissions
The Bangalore conference has issued a last-minute call for panel proposals as technical paper submissions for the US edition get set to open next week.
How to automate pre-tape-out ESD protection verification
A new paper describes an alternative to increasingly inefficient manual ESD verification that reduces risks of respins and missed delivery deadlines.
The road to ES Design West: Location, location, location
There's still plenty of time to build a busy and profitable agenda for a visit to ES Design West and SEMICON West in San Francisco next week.