EDA

An ESD Alliance panel on incoming Californian energy regulations originally scheduled for later this month has been postponed.

Three Mentor divisions - Embedded, PADS and Tanner EDA - will present their latest innovations during the conference and exhibition in Nuremberg next week.

Formal enables substantial fault pruning and more definitive fault injection for ISO 26262 using techniques such as sequential logic equivalence checking.

Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.

Analog fault simulation times have barely fallen for two decades but that is beginning to change.

StratoM hardware has 2.5B-gate capacity and can scale to 15B gates. Throughput claimed at 5X faster than earlier Veloce generation.

The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.

The major West Coast technical conference for lithography is just two weeks away and offers a packed agenda.

IoT edge designs are being undertaken by multi-disciplinary teams that must work within the tightest of budgets.

What's old is new: 200mm wafers are returning and driving shortages while 450mm fades into the distance.