EDA

Japanese giant uses variable thermal simulation on automotive IC intended for harsh environments.

Among the papers at this year's VLSI Symposia in Hawaii in June, Samsung will describe a 7nm CMOS process that uses EUV lithography to tighten up device features on minimum-pitch interconnects.

Racyics has kicked off a hosted-design service to make it easier for startups and researchers to access the 22nm FD-SOI process offered by GlobalFoundries.

NVMe is driving the SSD market thanks to its many useful features, but at least five major challenges must inform your verification plan.

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.

ARM is using technologies such as Hadoop and Spark to provide insight into how well its verification processes are working.

The first Chinese edition of Accellera's conference series takes place in Shanghai next Wednesday (April 19).

Cadence Design Systems has launched a design-rule checking engine that can distribute its workload across multiple servers in a cloud, private farm or mixture of both to speed up signoff.

Solido aims to bring the types of machine-learning techniques the company has used for its physical-analysis tools to a wider range of EDA tools through the launch of its ML Labs initiative.

Learn how to pre-empt timing and congestion issues that could arise after synthesis by using 'PlaceFirst' technology within Oasys-RTL.