VLSI Symposia issue calls for papers
Online paper submissions are now open for the 2017 Symposia on VLSI Technology and Circuits.
EDA
IMEC stacks nanowire transistors together on CMOS
IMEC has claimed at IEDM to have implemented for the first time the CMOS integration of vertically stacked nanowire transistors.
Siemens agrees deal to buy Mentor Graphics
German industrial conglomerate to pay $4.5B to extend its PLM division into electronic chip and systems design.
Webinar focuses on Eldo RF verification of Tanner-based designs
On-demand seminar explains how to exploit recently announced integration of Tanner and Eldo suites for sensor, IoT and other design types.
Cadence maps out safety plan for semiconductor-design tools
Cadence Design Systems is nearing completion of a program that will provide a portfolio of documentation for users of its tools who need to obtain safety approvals for their designs.
Serdes deal to push copper server interconnect to 100Gbit/s
A licensing deal with GlobalFoundries has provided chipmaker Aquantia with the ability to speed up development of a 100Gbit/s link technology for data centers.
7nm finFET process techniques lead IEDM lineup
At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.
Portable stimulus gears up to accelerate verification
Ahead of a tutorial on the technique at DVCon Europe with other EDA experts, Breker's Adnan Hamid talks about the need for portable stimulus in verification.
ESD Alliance to describe system shift at DVCon Europe
Electronic System Design Alliance executive director Bob Smith is to be be the keynote speaker during the DVCon Europe gala dinner.
Cadence packages VIP for ten protocols
Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.