Synopsys

September 9, 2013

SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy

Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , ,   |  Organizations: , ,
September 5, 2013

Real Intent CEO Prakash Narain on moving from RTL to SoC sign-off

Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
September 5, 2013

SNUG Boston focuses on challenges of gigascale IC design

Meeting focuses on advanced tools and techniques for the rapid development of gigascale ICs.
Article  |  Topics: Conferences, Blog - EDA  |  Tags:   |  Organizations: , , , , ,
August 29, 2013

IP providers make plans for the internet of things

ARM and Synopsys both plan to make inroads to the internet of things with their IP strategies.
Article  |  Topics: Blog - EDA, Embedded, IP  |  Tags: , , , , , , ,   |  Organizations: ,
July 8, 2013

Real Intent links tools to Synopsys flows through in-Sync program

Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
Article  |  Topics: Product  |  Tags: , , ,   |  Organizations: ,
June 17, 2013

Synopsys doubles speed of formal ECO checking

Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
Article  |  Topics: Design to Silicon, RTL, Verification  |  Tags: ,   |  Organizations: ,
June 14, 2013

Synopsys launches single kit to optimize IP across PPA

Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
Article  |  Topics: Digital/analog implementation, Blog - EDA, IP  |  Tags: , , , , , ,   |  Organizations: , ,
June 7, 2013

FinFET shift could drive analog automation as layout effects bite

The arrival of the finFET brings with it simulation and physical restrictions that might lead teams to resort to layout automation to get the job done.
June 3, 2013

UPF group moves to consider system-power issues

The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.
May 22, 2013

DAC 2013 Preview IX: Manufacturability

A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations: , , , , , , ,

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