September 9, 2013
Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
September 5, 2013
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
September 5, 2013
Meeting focuses on advanced tools and techniques for the rapid development of gigascale ICs.
August 29, 2013
ARM and Synopsys both plan to make inroads to the internet of things with their IP strategies.
July 8, 2013
Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
June 17, 2013
Incremental formal verification of ECOs makes finalisation of chip design process faster, more predictable.
June 14, 2013
Latest addition to DesignWare portfolio balances trade-offs across CPUs, GPUs and DSPs while automating custom design techniques such as multi-bit flip flops.
June 7, 2013
The arrival of the finFET brings with it simulation and physical restrictions that might lead teams to resort to layout automation to get the job done.
June 3, 2013
The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.
May 22, 2013
A look at what you can learn about design for manufacturability and yield at this year's Design Automation Conference