SNUG Boston focuses on challenges of gigascale IC design

By Luke Collins |  1 Comment  |  Posted: September 5, 2013
Topics/Categories: Conferences, Blog - EDA  |  Tags:  | Organizations: , , , , ,

The Synopsys Users Group conference series reaches the East Coast next week with SNUG Boston, to be held at the Newton Marriott Hotel on 12 September. The conference will include the usual mix of keynote speeches, user papers and tutorials, as well as a Designer Community Expo.

Aart de Geus, chairman and co-CEO of Synopsys will open the meeting with a keynote on the challenges that designers face in developing gigascale ICs in rapidly evolving markets, in which simply producing a better version of the current design may not be enough to meet the needs of the next-generation product. De Geus will argue that the only way to tackle such challenges is through greater collaboration between design groups and their ecosystem partners, and among the EDA, IP and service partners that support them.

A number of the user presentations and tutorials that follow will focus on ways to meet the challenges of gigascale design.

* Scott McCloskey of Qualcomm and Amzie Adams of Synopsys will talk about the challenges of moving from 28nm to 20nm processes, including coming to terms with double-patterning requirements and an order-of-magnitude increase in design rule complexity.

* On the verification front, Conor Byrne, Padraig Golden, Venkatesh Jakke of Intel will discuss dealing with the extra complexities introduced by using multi-voltage design techniques using the IEEE 1801-2009 (UPF2.0) standard.

Another presentation, from David Brownell of Analog Devices, addresses the difficult issue of objectively measuring the quality of a verification environment, especially in the context of increasing testbench size and complexity following the adoption of SystemVerilog and UVM.

A third presentation, by Courtney Schmitt of Analog Devices, and Manoharan Vellingiri and Alex Wakefield of Synopsys, will discuss a technique for closing coverage in a constrained random methodology by running a value (event) based simulation alongside a symbolic (equation) based simulation.

* A session on transistor-level static timing will highlight the lengths to which some designers are now having to go to achieve the performance they need. A team from AMD will discuss using NanoTime to accurately time dynamic circuits at the transistor level. In a separate presentation Maureen Ladd of Synopsys will discuss enhancements to NanoTime to support full-swing differential circuitry, as used in Serdes and similar designs.

There’s a full agenda for the meeting here and a registration page here.

* SNUG Boston will also feature a Designer Community Expo, where users will be able to get up close and personal with tools from a host of vendors.

Real Intent will be on hand to exhibit its two product families – Ascent products for functional verification before synthesis, and Meridian products for performing advanced sign-off verification on issues that cannot be tackled by simulation or static timing analysis.

The Ascent family includes Ascent Lint, a high-capacity linting tool that performs syntax and semantic checks on complex RTL; Ascent Implied Intent Verification, which uses automatic check formulation followed by deep-sequential formal analysis to do early functional verification; and Ascent X-Verification System, which detects and isolates X-propagation issues early in Verilog RTL.

The Meridian family includes Meridian CDC, which performs comprehensive structural and functional analysis to ensure that signals crossing between asynchronous clock domains of a design are received reliably; and Meridian Constraints, which helps manage constraints using constraint validation, template generation, coverage analysis, equivalence checking and timing exception verification.

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