14nm/16nm finFETs debut at IEDM

By Chris Edwards |  No Comments  |  Posted: December 16, 2014
Topics/Categories: Blog - EDA  |  Tags: , ,  | Organizations: , ,

The International Electron Device Meeting (IEDM) has once again provided a chance for the major chipmakers to go head-to-head with their latest processes. This time we get the ability to compare the 14nm/16nm generation finFET processes from Intel and TSMC, as well as a silicon-on-insulator (SOI) form of finFET process from IBM.

TSMC used the conference to describe the improved version of its first 16nm finFET process, using better transistors to increase switching speed by 15 per cent and reduce power by 30 per cent. Reliability improvements have also increased the ability to overdrive the transistors for speed by 70mV.

The Taiwanese foundry opted for a 48nm fin pitch, implemented using the pitch-splitting form of double patterning – the fin is defined by the sidewall deposited either side of a patterned mandrel. The gate pitch is 90nm, with the lowest metal layer pitch set at 64nm, implemented using double patterning. Single patterning is used for the next set of layers, with a pitch of 80 or 90nm.

Second generation

Intel’s 14nm process follows on from the company’s initial 22nm finFET process. To maintain a conventional shrink from the 22nm process, rather than building it on the framework of a 20nm process, the option taken by TSMC and others, Intel has set a fin pitch of 42nm, with a minimum interconnect pitch of 52nm. Intel is using self-aligned double patterning combined with immersion lithography to define these lower layers. The result, the company claims, is a process that maintains a 0.7 per cent scaling trend at the transistor level, although the situation for interconnect is more complex, with scaling compared to 22nm ranging between 0.65 and 0.78. The resulting scale factor for contacted gate pitch – which Intel has used for several generations as its favored metric for density improvements is 0.78.

Reflecting the complexity of routing with finFETs, the pitch of metal one is a comparatively relaxed 70nm whereas ‘metal zero’ or local interconnect is 56nm and metal two is 52nm – presumably to optimize pin access into standard cells. Air gaps were used in the interconnect to improve capacitance in the 80nm- and 160nm-pitch layers.

Changes to fin doping and the profile have managed to put the trend towards increasing variability into reverse. The variation of threshold voltage was improved twofold over the 22nm process, allowing lower minimum voltage.

SOI control

IBM’s SOI substrate overcomes the need to use heavy doping to act as a stop layer for the bottom of the fin – the oxide does the job.

Like the Intel process, IBM opted for a 42nm fin pitch, again using self-aligned double patterning, and tuned the fin height for server processors. Although taller fins lead to smaller RC delays, bigger fins cause higher active power consumption. However, IBM has not disclosed the height chosen. Intel chose a fin height of 42nm.

To provide for high-speed and low-power transistors, IBM used a dual work-function process for the metal gates rather than rely on doping to control the threshold voltage. Although IBM opted for a tighter fin pitch than TSMC, the company chose to start the metal layers at a pitch of 64nm.

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