Facing a future of dark silicon

By TDF Staff |  No Comments  |  Posted: June 2, 2015
Topics/Categories: Blog - EDA  |  Tags: , ,  | Organizations: ,

Have you noticed the trending triad of terms in recent semiconductor articles, namely, dark silicon, Dennard’s Scaling and (of course) Moore’s Law? For example, a recent Pacific Crest report cites studies that predict half of a chip’s processor core may have to ‘go dark’ at the 8nm node. According to the report, that looming ‘darkness’ was one of the reasons why Intel was interested in acquiring Altera’s programmable technology. The hope seems to be that FPGA architectures will help accelerate the computing power of high-end, low geometric node processors in the data center.

To make sense of such discussions, engineers must first understand three trending phrases:

  • Dark silicon –The quantity of silicon that cannot be powered-on at the normal operating voltage. According to some predictions, the amount of Dark Silicon may reach up to 50%-80% at 8nm nodes. Mitigating issues include the processor architecture, cooling technology, and application workloads.
  • Dennard’s Scaling – This observation stated that, as transistors get smaller, their power density stays constant. In other words, power usage of transistors stays in proportion with area or both voltage and current scale (downward) with length.
  • Moore’s Law – The number of transistors in an IC has doubled approximately every two years. More transistors on chips leads to increasing performance at typically less power and smaller areas.

Since 2005, at about 90nm, Dennard’s (supply voltage) scaling has deviated from its historic downward course. While transistors have continued to scale to smaller sizes, as predicted by Moore’s Law, Dennard’s Scaling has leveled off. This decrease in voltage scaling has resulted in increasing power densities across the SoC, which meant that not all of the transistors could be powered simultaneously at the same voltage operating level. Since microprocessors are clock-based systems, the end of Dennard’s Scaling has meant the end of clock scaling and hence the beginning of multicore designs which could operate at different clock frequencies. But even multicore scaling has limits and, more importantly, it doesn’t provide the same degree of benefit as voltage scaling.

Moore’s Law, on the other hand, is facing its own problems. During a recent SEMI Pacific Northwest Chapter event, Gary Bultman, senior VP, strategic development and emerging markets, Lam Research, put it this way: “Historically, we’ve been able to shrink the chip to get more transistors per unit area. Material and performance improvements have also occurred (from node to node), but ‘shrink’ has been the primary engine to drive down cost. However, the lithography roadmap appears stalled at 193nm for last 5 to 7 years.

“To keep Moore’s Law going, we’ve had to use multi-patterning (specifically, double-patterning) techniques, which are driving up costs. With logic we also see alternative designs coming in such as gate-all-around vertical transistors, which has the potential to further increase the transistor packing density. But overall there aren’t a lot of levers available to keep the traditional logic cost engine going. There are some projections that we have hit a minimum in terms of the cost per transistor somewhere between 14/16 and 20nm. And as we go to 10 and 7nm, the cost per transistor of advanced logic will actually begin to increase.”

What’s is the path forward? According to a somewhat dated but still relevant paper from the 38th International Symposium on Computer Architecture (ISCA ’11), the path forward will be difficult.

“Given the time-frame of this problem and its scale, radical or even incremental ideas simply cannot be developed along typical academic research and industry product cycles. On the other hand, left to the multicore path, we may hit a ‘transistor utility economics’ wall in as few as three to five years, at which point Moore’s Law may end, creating massive disruptions in our industry. Hitting a wall from one of these two directions appears inevitable. There is a silver lining for architects, however: At that point, the onus will be on computer architects – and computer architects only – to deliver performance and efficiency gains that can work across a wide range of problems. It promises to be an exciting time.”

If these predictions prove accurate, then it will be left to architects to overcome the scale-less dragon of dark silicon. Otherwise, the cost for single-digit nanometer chips will rise for the first time since the beginning of the solid state industry.

Originally published on IP Insider at chipestimate.com

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors