EDA

StratoM hardware has 2.5B-gate capacity and can scale to 15B gates. Throughput claimed at 5X faster than earlier Veloce generation.

The major verification conference is looming and Mentor's participation will include tutorials that explore the latest in portable stimulus, SystemC, VIP and more.

An eight-part battleplan can help automate one of tougher electrical design challenges.

The major West Coast technical conference for lithography is just two weeks away and offers a packed agenda.

Five steps you can take to speed up the FPGA implementation of a complex design, from structuring your design flow to debugging its output.

IoT edge designs are being undertaken by multi-disciplinary teams that must work within the tightest of budgets.

DesignCon 2017 takes place from Jan 31 to Feb 2 at the Santa Clara Convention Center with its usual focus on PCB design and implementation.

Case study applies virtual prototyping to optimise address mapping, clock frequency, and Quality of Service configurations to meet DDR performance goals.

SoC security strategies, costs and trade-offs are analysed in this detailed webinar.

DDR memory subsystems need careful optimisation as demands on memory grow more rapidly than off-chip bandwidth.