DesignCon 2016 preview: Mentor Graphics
HyperLynx leads the way for vendor at DesignCon with booth demos and a day-long modeling and analysis seminar.
Archives
Qt tightens open-source licenses
The Qt Company has changed the licenses it supports on the open-source versions of its user-interface software framework, removing the LGPL2.1 version.
Prpl Foundation proposes security architecture
The Prpl Foundation has published a guide to techniques it claims will improve the security of embedded systems.
Accellera and Mentor’s Dennis Brophy talks standards targets and DVCon
Driving down energy consumption for the IoT, making portable stimulus deliver real benefits and the practical benefts of a globalizing DVCon.
GaN power makes progress at IEDM 2015
Researchers describe at IEDM 2015 how they are making gallium nitride fit into a wider range of power-handling applications and may even result in mass-market vertical transistors.
IEDM keynote: cost scaling will swap architectural changes for area
According to ARM's Greg Yeric in his keynote at IEDM, even with cost improvements for multiple patterning, fewer designs will see the benefit of further silicon node scaling. Savings will come from design.
Asymmetric variability issues could impact 7nm processes
Simulation shows 7nm process will need tighter variability control than expected, and possibly accommodation for asymmetric variability
Cadence partners for photonic IC design
Cadence Design Systems has worked with Lumerical Solutions and PhoeniX Software to develop a flow for designing photonic ICs based on the Virtuoso custom-design platform.
Three key ways to reduce silicon test costs
Mentor's Greg Aldrich describes how test's market leader is driving down cost in the billion-gate era by rethinking and extending existing technologies
Ultrasoc tweaks debug technology to act as SoC burglar alarm
Ultrasoc is adding security monitoring to its toolkit, providing SoC designers with a mechanism for their chips to warn of attempts by hackers to break into secure areas.