Accellera signs off on SystemC control standard
Accellera has published version 1.0 of the SystemC Configuration, Control and Inspection (CCI) standard.
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Case study demonstrates 59% extra power savings for HPC
Taiwanese ASIC specialist Alchip discusses use of Mentor PowerPro for low power on 16nm 24x24 array HPC chip in detail
Pillar transistor points to smaller SRAMs at 5nm
Imec and Unisantis Electronics have developed a process flow based on a vertical transistor with a gate on all sides they claim will lead to denser memories on a 5nm node.
Arm Cortex-A processor team focuses on formal
Arm is on the way to making formal a fundamental part of its verification strategy for ARM Cortex-A processors.
IEDM 2018 aims to span quantum, neuromorphic and CMOS devices
IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.
Synopsys offers ASIL D ready embedded vision IP for ADAS and autonomous vehicle SoCs
Synopsys has extended its range of semiconductor IP for use in advanced driver assistance (ADAS) and autonomous vehicle SoCs with the launch of embedded vision processor blocks that have been given safety enhancements.
Mixed-signal circuits push scaled CMOS at VLSI
The circuits sessions at mid-June's VLSI Symposia in Honolulu feature a number of papers that improve the performance of scaled mixed-signal processes.
Motion harvester wins MEMS design contest
Energy harvesting, mechanical reprogrammable logic, and genetic algorithms were among the finalists for the MEMS design competition.
Cadence opens three fronts on mixed-signal failures
Cadence has started the rollout of a set of design tools for mixed-signal reliability analysis.
7nm process with EUV to feature at VLSI
Samsung Electronics will describe at the upcoming VLSI Symposia how its engineers have applied EUV to a variety of layers in a 7nm finFET process.