TSMC certifies Synopsys tool flow for 7nm EUV process
New flow enables high-performance, high-integration designs.
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User2User Silicon Valley rolls out later this month
Mentor's west coast user conference will take place in Santa Clara on May 15. Attendance is free-of-charge.
Andes teams with Imperas and UltrasoC for RISC-V
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
Combining tools and services for evolving automotive design flows
Automotive companies need to partner closely with tool suppliers as design processes are disrupted by new technologies.
Anne Cirkel recognized for advancing role of women in electronics design
Mentor executive, former Design Automation Conference chair and Tech Design Forum journal founder to receive Marie R. Pistilli Award at DAC 2018.
SEMI-ESDA tie-up aims to extend EDA’s global reach
Cooperation in key verticals such as automotive and changes for DAC as well as global conference outreach underpin EDA association's move.
Free formal verification primer offered by Synopsys
Free e-book offers an introduction to formal verification methods for those who may be curious about the technique, or who need to understand its advantages and limitations in order to manage its use effectively.
Tensilica DSP extends pipeline for performance
Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.
Cadence tunes Virtuoso for 5nm and SIP
Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
Control test point counts for ISO 26262
The automotive safety standard targets 90% in-system test coverage. VersaPoint technology helps to simplify reaching your target.