Archives

At IEDM this year, Macronix showed how a 3D architecture may bring back NOR flash, which stopped scaling a decade ago.

Imec's senior vice president of CMOS outlined future directions for the technology over the coming decade.

Mentor, a Siemens business, has rebranded as Siemens EDA, almost almost four years after the EDA company was acquired.

Aldec updates tools to add support for the latest release of the VHDL verification methodology.

Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.

Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.

Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.

Accellera Systems Initiative has published for open review version 2.0 of the Portable Test and Stimulus standard.

This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.

A partnership between Siemens and VSI, a real-world autonomous vehicle research company, aims to refine and promote digital twin strategies.