How to simplify ESD verification with pre-coded checks
Electrostatic discharge verification is becoming increasingly hard to achieve but automated pre-loaded checks can now help.
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How to use virtual mode in emulation
Virtual strategies make for greater productivity and widen the number of emulation use cases. A new paper considers some of the most popular examples.
Strong growth forecast for IC industry on tight capacity, pent-up demand
Pent-up demand and mis-timed capacity investment could cause rapid IC industry growth.
Design house recommends earlier start to flip-chip bump layout
Design-services company Sondrel is recommending teams start earlier on package design to avoid delays after IC tapeout.
Copper’s future is troubled but it’s likely to stick around
The metal has done sterling service for 20 years but the time is approaching to find a replacement for copper as problems with parasitics continue to build up, work presented at last month’s IEDM shows. But it's not an obvious switch.
A new methodology addresses the increasing challenge of reset domain crossing
Originally presented at DVCon Europe, a new paper automates complex steps in RDC verification and reduces noise.
Plasmonics may point way to faster interchip comms
Work by the University of Toronto and Arm presented at IEDM indicates plasmonics could be a viable contender for high-speed chip-chip communications.
Backside metal defends against IR drop and side-channel attacks
Work presented at IEDM 2020 shows taking advantage of the IC backside for power and ground for the additional area can deliver further benefits for IR drop and security.
Virtual emulation delivers verification for the latest storage devices
Computational storage devices are posing a new raft of challenges that is being addressed using a powerful pre-silicon methodology.
Arm expands cloud migration on Arm-based machines at AWS
Arm is pushing more work onto Arm servers in the AWS cloud as it encourages EDA vendors to port their tools to the architecture.