Aldec has updated its Riviera-Pro suite to include the 2020.08 revision of the open-source VHDL verification methodology (OSVVM), providing access to the requirements tracking, updated scripting, and model-independent transaction elements of the methodology.
The latest version of Riviera-PRO (release 2020.10) also includes SystemVerilog and VHDL-2019 simulation enhancements. For SystemVerilog, the enhancements include extended support for four-state integral packed unions, two-state integral packed vectors, structures and unions, and fixed-size unpacked vectors, structures and unions. For VHDL-2019, the enhancements include support for arrays and records of protected types.
“In terms of VHDL-2019 support, Aldec is well ahead of the game,” claimed Jim Lewis director of VHDL training at SynthWorks and IEEE 1076 VHDL Working Group Chair. “The company’s Riviera-PRO introduced several VHDL-2019 support features back in June 2020, and the enhancements announced today will facilitate the development of advanced verification capabilities.”
Debugging and performance enhancements have also been added to the 2020.10 release. These include support for new coverage pragmas within the Verilog compiler and randomization performance enhancements.