DAC 2018 preview: Verific

By TDF Staff |  No Comments  |  Posted: June 18, 2018
Topics/Categories: Blog Topics  |  Tags: , , ,  | Organizations:

Verific, the specialist in SystemVerilog, VHDL and UPF parser platforms, is exhibiting on Booth #2311 during this year’s Design Automation Conference at Moscone West, San Francisco (Exhibition dates: Jun 25-27).

The company will demonstrate its existing parser platforms, alongside the ‘Verific with INVIO’ integration announced in May.

The INVIO platform resides on top of Verific’s standard parsers and provides high-level level Python and C++ APIs that enable users to simplify and streamline their design environment, thereby accelerating tool development. INVIO’s APIs are SystemVerilog- and VHDL-language agnostic and also support UPF and Liberty.

The company acquired the INVIO portfolio and its development team from Invionics Software in 2017.

Attendees who visit the Verific booth can pick up this year’s giveaway giraffe and the company is also sponsoring ‘Verified’, a celebration of the verification ecosystem. The event takes place on Monday, June 25, at the Golden Gate Tap Room from 8:00pm until midnight and a limited number of tickets will be available at the Verific booth.

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