DAC 2019 preview: Verific Design Automation

By TDF Staff |  No Comments  |  Posted: May 20, 2019
Topics/Categories: Conferences, Blog - EDA, - Tool development, Verification  |  Tags: , , , ,  | Organizations: ,

Parser specialist Verific Design Automation will mark the 20th anniversary of its foundation at the 2019 Design Automation Conference in Las Vegas next month.

DAC will take place at the Las Vegas Convention Center from June 2-6, and Verific will exhibit at Booth #638 (the exhibition runs June 3-5 from 10:00AM-6:00PM).

Verific’s applications and R&D staff will be demonstrating and available to discuss the company’s SystemVerilog, VHDL and UPF parsers, and their use in the simplified and accelerated development of EDA software.

The company also now offers the ‘Verific with INVIO’ platform. DAC demonstrations of the platform will illustrate how its SystemVerilog and VHDL language-agnostic Python and C++ APIs also simplify and streamline tool development.

As regular DAC attendees will know, Verific is also known for its giraffe giveaways and, as it marks a milestone birthday, 2019 will be no exception. Just look for the rather bigger giraffe poking its head out from atop a booth marked – you guessed it – “Head and shoulders above the rest.”


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