DVCon USA 2019 preview: Verific Design Automation

By TDF Staff |  No Comments  |  Posted: February 21, 2019
Topics/Categories: Blog - EDA, - Tool development  |  Tags: , , , , , ,  | Organizations: ,

Verific Design Automation, specialist in parsers for SystemVerilog, VHDL and UPF, will exhibit at DVCon USA next week (Doubletree Hotel, San Jose, February 25-28).

The company will demonstrate all of these products and its Verific with INVIO platform. The INVIO platform resides on top of the company’s standard parsers and provides high-level level Python and C++ APIs to simplify and streamline a Verific user’s design environment and thus accelerate tool development.

Its APIs are SystemVerilog- and VHDL-language agnostic and also support UPF and Liberty.

Attendees will be able to find Verific  at Booth #705. Look out for the giraffe peaking over the top of the company’s logo and the tag line, “Head and Shoulders above the Rest.”

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