Taking risk out of software-driven networking SoCs
How virtualization and integration with hardware testers are enabling networking SoCs in the billion-gate era.
The adoption of software-driven networking (SDN) architectures is being driven by markets such as cloud computing, data centers, and mobile communications. SDNs dramatically push SoC complexity, size, and port count. This poses many challenges to teams developing and verifying these monster designs.
Figure 1. Complexity and gate counts increases due to SDN architectures (Mentor Graphics)
The challenges presented by designs such as networking SoCs cannot be addressed by traditional software-based simulation or formal verification. In the billion-gate era, hardware emulation is the only technology that can take on these tasks.
Mentor Graphics’ Veloce emulation platform provides virtually unlimited capacity to emulate the largest designs, and total design visibility and access/control without instrumentation/compilation. It also supports high throughput, along with fast, predictable compile and bring-up time, and accommodates multiple concurrent users with high resource utilization. Veloce can be deployed in several modes to perform different verification tasks.
Virtualizing networking SoC challenges
Design teams verifying networking SoC designs with many ports are moving from traditional in-circuit emulation (ICE) to a virtual verification environment. This eliminates hardware and hardware drawbacks such as noise, power, cables, reliability and associated cost. Virtual devices can be built before actual hardware is available using a combination of software and synthesizable hardware models. These run at emulation speed, support multiple users and multiple projects, can be accessed remotely, and deployed in data centers.
However, the virtual mode requires the creation of a virtual test environment. This is no trivial task. With that in mind, Mentor has developed a comprehensive virtual environment, Veloce VirtuaLAB, to support pre-silicon testing of application-specific SoC designs.
For networking SoCs specifically, VirtuaLAB includes an Ethernet Packet Generator and Monitor (EPGM) that generates, transmits and monitors Ethernet packets to-and-from the design under test (DUT). It can configure from 1GE to 400GE ports using xMII and PCS interfaces.
Each VirtuaLAB supports up to 32 ports. Multiple VirtuaLAB instances can be assembled to expand the port count to greater than 1,000. Figure 2 compares an Ethernet ICE setup with a VirtuaLAB equivalent for testing a 128-port Ethernet switch.
Figure 2. Comparing an Ethernet ICE setup against a VirtuaLAB setup for a 128-port Ethernet switch (Mentor Graphics)
As powerful as VirtuaLAB is for pre-silicon verification, when applied to post-silicon testing its effectiveness is limited.
Bridging the gap for networking SoCs
Instead, the methodology for testing networking engineering samples in the lab is based on dedicated networking tester hardware.
In this scenario, the verification flow has two gaps. The first is between simulation and emulation. The second gap is between pre-silicon verification and post-silicon testing. Mentor has bridged these gaps by entering into an agreement with tester hardware specialist IXIA. IXIA products cover the range of networking test needs, from performance, to functional, to security and conformance testing, including physical testers and virtual testers.
Mentor and IXIA have jointly integrated IXIA’s IxNetwork Virtual Edition (VE) and the Veloce Virtual Network (VN) App, as shown in Figure 3.
Figure 3. Block diagram of the Mentor/IXIA networking integrated solution (Mentor Graphics/IXIA)
The front-end, IxVerify, is based on IXIA’s IxNetworkVE test products. It uses the same GUI and enables reuse of test scripts and functionality. The customer experience is the same as that IXIA customers have today, but also provides clock-accurate precision advantages that traditional virtual platforms lack.
The partnership between Mentor and IXIA allows networking customers to seamlessly integrate an IXIA virtual environment into an emulation-based verification flow, bringing the powerful advantages of emulation to the lab environment. For networking SoCs, this allows for the reuse of traffic flow generation scripts for greater efficiency and improved debug, faster time-to-market, and gives design teams the ability to de-risk the challenges of complex chip designs.
Further reading
To learn more about the partnership between Mentor Graphics and IXIA, download this whitepaper: Mentor Graphics and IXIA De-Risk Networking SoC Verification.
About the author
Ron Squiers is a solutions architect who is passionate about innovation, strategic product development and positioning in the networking domain. He has developed next generation networking, communications and encryption products for Mentor Graphics, Broadcom, Hewlett Packard, SGI, AMD and several startups. Ron received his BSEE from the University of California at Berkeley and graduate studies at Stanford University.
