UltraSoC scales up debug architecture

By Chris Edwards |  No Comments  |  Posted: February 18, 2019
Topics/Categories: Blog - IP  |  Tags: , ,  | Organizations:

UltraSoC has increased the capacity of its embedded analytics architecture to encompass large-scale manycore architectures and to deal with heavy bursts of activity that will come from multiple probes.

One key change is an extension to the address range of the on-chip probe and processing elements. Whereas the previous version had a limit of 256 elements, due to the use of 8bit address registers, this limitation has now been removed. In principle, the address range is unlimited but, for most implementations, the IP will be deployed with 16bit address support to handle more than 60,000 elements.

As well as the address-range increase, the company has made changes to its System Memory Buffer (SMB) IP to support the hierarchies that now feature in manycore systems. This allows SMBs to be placed at multiple levels within the hierarchy to support processor clusters and superclusters.

Dave Ditzel, founder and CEO of Esperanto, said: “Esperanto’s mission is to enable the most energy-efficient high-performance computing systems for artificial intelligence, machine learning and other emerging applications. That requires us to put over a thousand RISC-V processors and AI/ML accelerators on a single chip; UltraSoC’s ability to match that level of scaling with monitoring, analytics and debug capabilities is a vital enabler for our business.”

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