Andes teams with Imperas and UltrasoC for RISC-V

By Chris Edwards |  No Comments  |  Posted: May 1, 2018
Topics/Categories: Blog - EDA, IP  |  Tags: , , , ,  | Organizations: , ,

Ahead of the RISC-V Workshop in Barcelona next week (May 7, 2018), Andes Technology has inked deals with two suppliers to help support SoC development. Andes has picked UltraSoC for trace and debug technology and extended its relationship with simulation specialist Imperas Software.

Andes said it will use UltraSoC’s IP to help enhance debugging on embedded products built around the RISC-V cores in applications such as AI, computer vision, network controllers, and storage. Imperas has developed models for two of the latest RISC-V cores: the N25 and the 64bit NX25, and which include simulations of the V5m extensions.

“The momentum for RISC-V is accelerating, and Andes is the first established CPU IP vendor to offer a RISC-V processor for licensing. We are pleased to support their new AndeStar V5m extensions in the OVP models of their 32-bit/64-bit CPU cores, based on RISC-V,” said Simon Davidmann, president and CEO of Imperas.

The Extendable Platform Kits (EPKs) for Andes cores run FreeRTOS, and also support heterogeneous designs with mixtures of Andes processors and other vendors’ cores including application processors.

The partnership with UltraSoC allows customers for Andes V5 N25 and NX25 processors to have advanced embedded analytics capabilities integrated as an option. Charlie Su, CTO and senior vice president of Andes, said the company already has a number of customer engagements based on the N25 and NX25 that will use UltraSoC’s debug technology.

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