DVCon USA 2019 preview: Mentor

By TDF Staff |  No Comments  |  Posted: February 11, 2019
Topics/Categories: Blog - EDA, - Verification  |  Tags: , , , , , , , , ,  | Organizations: , , , , ,

DVCon USA begins in two weeks (February 25-28) at the Doubletree Hotel in San Jose, California. Mentor, a Siemens business, is participating across the conference in technical sessions, a panel, a keynote and more as well as exhibiting at Booth #1005. Main products for Mentor at DVCon include Catapult HLS and PowerPro analysis, the Questa simulation and verification suite, the Veloce emulator family, and the Visualizer debug environment.

Some of its main activities are summarized below:


The industry continues to ascend the formal verification learning curve, though at a now much faster pace. A Mentor workshop on Monday (Feb 25), ‘It’s Been 24 Hours – Should I Kill My Formal Run?’, illustrates this by asking not whether or not to use formal but rather how far you should go. Key issues to be covered in the 90-minute session are:

  • How you can set yourself up for success before you kick off the run by writing assertions, constraints, and cover properties in a “formal friendly” coding style
  • What types of logic in your DUT will likely lead to trouble (in particular, deep state space creators like counters and RAMs), and how to effectively handle them via non-destructive black boxing or remodeling
  • Matching the run-time multicore configuration and formal engine specifications to the available compute resources
  • Once the job(s) start, how to monitor the formal engines’ “health” in real time
  • Confirm the relevance of the logic “pulled in” by your constraints
  • Show how a secure mobile app can be employed to monitor formal runs when you are away from your workstation
  • Examine whether a run’s behavior is consistent with the expected alignment between the DUT’s structure and the formal engines’ algorithmic strengths
  • Leverage all of the above to make the final “continue or start over” decision

Monday, February 25, 3:30-5:00pm, Fir


Fram Akiki, vice president for the Electronics Industry at Mentor’s parent Siemens PLM, will deliver the Tuesday (Feb 26) DVCon USA keynote, ‘Thriving in the Age of Digitalization’. It will explore how trends in fields such as AI and 5G combined with new market entrants applying disruptive models are driving a need through integrated digitization strategies across the semiconductor supply chain.

Tuesday, February 26, 1:30pm-2:30pm, Oak/Fir


AI is having increasing influence on chip design, presenting a number of design and verification challenges in respect of the technologies and platforms used. Emulation is proving key to this process.

Jean-Marie Brunet, marketing director of Mentor’s emulation business, will moderate a DVCon USA panel on Wednesday (Feb 27), ‘Deep Learning –– Reshaping the Industry or Holding to the Status Quo?’, with contributions from AMD, Achronix Semiconductor, Nvidia and others, looking at how they aim to reach their AI project objectives.

Wednesday, February 27, 1:30pm-2:30pm, Oak/Fir

Technical papers

Mentor has papers stretching across five sessions within the main DVCon USA programme, and a further six publications during the poster session on Tuesday (Feb 26)

Main conference

(click on the links below for details of location and other presentations in the relevant sessions).

Tuesday, February 26, 3:00pm-4:30pm

5.1 UVM IEEE Shiny Object

5.3 Fun with UVM Sequences – Coding and Debugging

Wednesday, February 27, 10:00am-12:00pm

9.2 A Systematic Take on Addressing Dynamic CDC Verification Challenges

9.3 Using Modal Analysis to Increase Clock Domain Crossing (CDC) Analysis Efficiency and Accuracy

10.1 Unleashing Portable Stimulus Productivity with a PSS Reuse Strategy

10.2 Results Checking Strategies with the Accellera Portable Test & Stimulus Standard

Wednesday, February 27, 3:00pm-4:30pm

11.1 Supply Network Connectivity: An Imperative Part in Low Power Gate-level Verification

12.2 Formal Bug Hunting with “River Fishing” Techniques

Poster session

Tuesday, February 26, 10:30am-12:00pm, Gateway Foyer

  • SystemC FMU for Verification of Advanced Driver Assistance Systems
  • Transaction Recording Anywhere Anytime
  • Multiplier-Adder-Converter Linear Piecewise Approximation for Low Power Graphics Applications
  • Verification of Accelerators in System Context
  • Introducing your Team to an IDE
  • Moving Beyond Assertions: An Innovative Approach to Low-power Checking using UPF Tcl Apps



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