AI

Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.

Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.

Menta eFPGA IP is highly configurable making it well suited to the evolving designs that exploit HLS abstraction.

Do China's ambitions as a world-class innovator face fundamental challenges as a result of the sector's existing economic infrastructure?

DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.

A recent white paper from Synopsys outlines the complexities of developing hardware for use in machine-learning and artificial-intelligence (AI) systems.

For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design, thanks to the rise of AI.

Synopsys applies AI to speed PrimeTIme, as part of wider strategy to exploit machine learning to ease chip design

IEDM has issued a call for papers for its 2018 conference, expecting to cover devices and circuit interactions in neuromorphic, quantum and conventional computing.

DAC in June will feature a series of keynotes and technical sessions on machine learning and AI for both target applications and in the design process itself.