AI

February 12, 2020

AI processor company opts for Analog FASTSPICE and Symphony

Mythic will use the Mentor tools for its analog-targeted intelligence processing units.
February 10, 2020

Arm adds AI to Cortex-M cores

Arm has launched a pair of cores intended to bring acceleration for machine learning to its Cortex-M series of processors.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
December 16, 2019

Mentor delivers eMRAM test for ARM/Samsung FDSOI at 28nm

Tessent test suite targets automotive, AI and IoT projects that need embedded non-volatile memory.
November 12, 2019

Xilinx aims for software flow with Vitis

Xilinx has released the first version of its Vitis development environment as the company aims to capture a user base that is more used to software than hardware tools.
Article  |  Topics: Blog - Embedded  |  Tags: , , , ,   |  Organizations:
September 4, 2019

IEDM homes in on connected devices

The IEDM has chosen a theme based around technologies for connected devices for its upcoming conference in December.
Article  |  Topics: Blog - EDA  |  Tags: , , ,
August 23, 2019

Making the case for HLS in autonomous drive

The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
July 3, 2019
IBM Q

Roadmapping the quantum realm

The US Quantum Economic Development Consortium is looking to stimulate a supply chain and technology infrastructure for quantum computing, with more about its efforts due to come out in the next few days.
July 2, 2019

Verifying in an HLS context for AI and ML designs

A SystemC/C++ app from a library that extends the OneSpin 360 DV-Verify platform was used by ML IP specialist NanoSemi on a 5G/WiFi project.
June 27, 2019

Building an ecosystem around HLS for AI and ML designs

Mentor's AI Accelerator Ecosystem adds reference designs, libraries and other forms of support around its Catapult HLS platform.
April 16, 2019

Boost your DFT efficiency for AI silicon design

Three hierarchical DFT strategies help cut time-to-market for large AI chips by exploiting regularity and addressing test at the RTL.
Article  |  Topics: Blog Topics, Tested Component to System  |  Tags: , , , , , ,   |  Organizations:

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