Use equivalence checking to retarget obsolete FPGA designs
Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
Author Archives: TDF Editor
Parasitic extraction challenges intensify for 5G
5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.
Cybersecurity must be built in not bolted on
Learn how one of the leading tool vendors addresses the security of its products and customer data through a ground-up cybersecurity strategy.
Navigate variables and lifetimes in SystemVerilog
Variable lifetimes are an apparently basic but also tricky feature within the verification language.
Go inside proposals for common chiplet models
Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.
Verifying the new namespace storage options in NVMe 2.0
The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
Learn strategies for better measurement and test in simulation-based PCB design
A new white paper offers useful tips and techniques for PDN analysis and performance optimization in designs such as those using DDR4.
Capturing connectivity for assembly verification in 2.5D and 3D design
Learn how to ingest data from multiple engineering teams in multiple formats on interposer and other multi-dimensional projects.
How digital twin evaluations optimize STCO-based design
System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
Choose the right advanced packaging methodology for metal fill rules
Advanced packaging requirements from foundries and OSATs pose stringent challenges. A new paper describes three ways of satisfying them.