Author Archives: TDF Editor

About TDF Editor

The head honcho
October 11, 2021

ITC 2021 preview: Siemens Digital Industries Software

Packetized test and three new technologies provide the core of the company's DFT presentations during the virtual International Test Conference running this week.
Article  |  Topics: EDA - DFT, Blog - EDA  |  Tags: , , ,   |  Organizations: ,
September 28, 2021

Scaling power integrity analysis to match analog content in today’s designs

Siemens introduces mPower to bridge the analog-to-digital gap in IR-drop and EM analysis, reflecting the scaling trends in today's ICs.
September 17, 2021

Digital twins manage change in E/E design for aerospace

A three-pronged digital twin strategy can help aviation and defense companies master increasing complexity in electrical implementations.
August 18, 2021

Practical steps toward ECAD-MCAD integration for automotive design

The need for the electrical and mechanical design domains to inform one another in more detail is recognized, but how do you do it?
Article  |  Topics: Blog Topics  |  Tags: , , , , ,   |  Organizations:
July 26, 2021

Learn how to apply formal verification to safety-critical aviation designs

A detailed technical overview of formal verification within the context of the DO-254 (ED-80) standard is now available to download.
Article  |  Topics: Verification  |  Tags: , , , , , , ,   |  Organizations:
July 16, 2021

How to meet formal embedded software guidance for medical devices

Vulnerabilities in connected healthcare products have led medical requlators to issue further security recommendations for their design and maintenance.
Article  |  Topics: Blog - Embedded  |  Tags: , , , , ,   |  Organizations: ,
June 21, 2021

From iterative to in-design DRC and debug for place and route

Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
May 28, 2021

Would you prefer a hypervisor or a multicore framework?

Determining which embedded technique to adopt is more than just a question of what cores the system has.
May 28, 2021

PCIe 6.0 gets verification IP as formal arrival approaches

Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
Article  |  Topics: Blog - EDA, IP, - Verification  |  Tags: , , , , , , ,   |  Organizations: ,
May 14, 2021

How MaxLinear cut physical verification time with in-design DRC

A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.