eSilicon offers ‘no gain, no pain’ ASIC block optimisation service

By Luke Collins |  No Comments  |  Posted: May 19, 2015
Topics/Categories: Design to Silicon, Blog - EDA  |  Tags: ,  | Organizations:

ASIC design and manufacturing services company eSilicon is offering to analyze blocks within an ASIC design to see whether it could improve their performance. If its automated tools can see ways to improve the blocks by an agreed amount of power, performance or area, the customer can contract with eSilicon to do the work. If not, there’s no charge.

The move is part of the company’s ‘design virtualisation’ strategy, which has seen it automate and bring online various steps within the process of designing an ASIC and having it made, packaged and tested.

Mike Gianfagna, vice president of marketing for eSilicon, said “the industry needs better design virtualisation across the board because customers are making bet-the-company decisions with limited information.”

Gianfagna argues that by ‘virtualising’ design, that is decoupling choices about issues such as operating conditions, IP choices, process options, Vt mixes, cell libraries and so on, into a separate part of the development process, it will be possible to avoid making overly constraining decisions too early in the process.

“With design virtualisation you are not bound to those decisions once and for all,” he said. Instead eSilicon can search its database of completed designs and design scenarios and offer answers to multiple ‘what if’ questions about these choices. Gianfagna says that when eSilicon computers are not working on an immediate problem, they run design scenarios to fill out the database. At advanced nodes, even down to 14nm, Gianfagna argues that interpolations between the limited number of designs and scenarios that they have run so far are “a whole lot better than the guesswork people have been using so far.”

The new Optimizer service is meant to address ‘problem’ blocks in customer ASIC designs, in two stages. The first is a check on the design RTL pre-synthesis to ensure it is clean and internally consistent. The second involves a consultation with the customer to find out which parameters they want to improve on their problem block. The Design Optimizer can then do trial physical implementations to see whether it can deliver that improvement.

“The customer has a pay-for-results engagement with us,” Gianfagna said, and if they don’t have time to implement the suggested changes, eSilicon can offer that service.

eSilicon is also rebranding its online ASIC design and manufacturing platform.

The eSilicon STAR (for self-service, transparent, accurate, real-time) platform supports eSilicon’s existing IP browsing, instant quoting and work-in-process tracking capabilities along with the new chip optimization offering.

The platform also delivers an enhanced user interface with simplified account setup and access. The point tools have been renamed, as follows:

  • Navigator: search, select and try eSilicon IP online
  • Optimizer: self-service IC design optimization for PPA
  • Explorer: evaluate options and get fast, accurate quotes for MPW and GDSII handoffs
  • Tracker: real-time design progress and IC delivery tracking, including order history, forecasts and yield data

The eSilicon STAR platform is available now. Users can register for an account through eSilicon’s online registration interface.

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