imec and Coventor partner for 7nm process development

By Luke Collins |  1 Comment  |  Posted: October 28, 2014
Topics/Categories: Design to Silicon  |  Tags: , , , ,  | Organizations: ,

imec, the Belgian nano-electronics research centre, has partnered with Coventor, a process development tool supplier, to work on 10nm and 7nm processes.

The two organisations are using Coventor’s SEMulator 3D virtual process development tool to explore layout options, process step performance and control methodology for these advanced processes.

SEMulator3D enables users to model and simulate manufacturing effects in software before committing to test chips.

At imec, process and integration specialists have linked optical lithography simulations with SEMulator3D to explore finFET scaling to the 7nm node, and to compare the process window margins for several dense SRAM designs that will use spacer-assisted quadruple patterning and either multiple immersion or EUV patterning cut/keep solutions.

The team has also developed a spacer-assisted quad patterning scheme for 7nm dense interconnect, and analysed process window margins for an immersion-based multiple block patterning solution. Future collaboration will focus on modeling directed self-assembly for advanced patterning.

An Steegen, senior vice president process technology at imec, said: “A virtual fabrication platform enables us to tie together integrated processing before all of the individual processes are available. The SEMulator3D tool gives us the visibility and accuracy to do that, and an integrated platform to bring together all the various elements of advanced processing before moving on to actual silicon.”

David Fried, chief technology officer, semiconductor, at Coventor, said: “This collaboration allows us to synchronize our modeling roadmap with one of the industry’s most advanced process roadmaps, as well as to speed the development of their 10nm and 7nm technology.”

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