November 30, 2018
Workhorse synthesis tool updated to make it suitable for use on designs at process nodes of 5nm and below.
November 27, 2018
Fusion Compiler uses a single, scalable data model, updated optimization engines, and an analysis backbone based on the industry's golden sign-off tools.
November 15, 2018
Mentor's flagship PCB suite is aiming to offer another 'shift left' in verification as respins rise.
November 14, 2018
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
November 13, 2018
Accellera has updated the reference implementation for the Universal Verification Methodology to reflect the changes made for the latest release of the standard.
November 7, 2018
Mentor's updated AMS platform claims performance boost by obviating 'legacy' technology.
November 6, 2018
Data-center networking specialist Netronome has recruited a number of silicon makers and IP suppliers to a standard for chiplet designs that can be used in SIPs for edge computers and servers.
October 31, 2018
Cadence has added direct support for neural networks to the latest iteration of its DSP cores aimed at audio systems.
October 22, 2018
CMOS moving to 3nm and DRAM going beyond 20nm scaling are two of the late papers at the upcoming IEDM and part of a larger examination of semiconductor trends.
October 17, 2018
Next week's DVCon Europe conference in Munich will tackle a range of topics, from analog verification to the use of machine learning for functional verification, backed up with case studies on the use of TLM and SystemC in live projects.