Closing code coverage with a hardware-aware HLS-to-RTL flow
Closing code coverage from HLS has been tricky because the C++ tools were built for software not hardware. But that is changing.
Blog Topics
IEDM shows progress on embedded eMRAM
Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power.
Microchip opts for RISC-V cores in SoC FPGA
Microsemi has put multiple RISC-V cores into a new generation of SoC FPGAs, intended for embedded systems that need to run Linux.
Leti takes the heat off monolithic 3D
CEA-Leti claimed at IEDM to have achieved major steps in bringing monolithic 3D integration closer to production readiness.
Achronix builds machine learning IP into eFPGA
Achronix has incorporated direct support for machine learning into the latest version of its eFPGA architecture.
Design Compiler updated for 5nm and beyond
Workhorse synthesis tool updated to make it suitable for use on designs at process nodes of 5nm and below.
Synopsys fuses synthesis and place-and-route to improve IC design quality and time to results
Fusion Compiler uses a single, scalable data model, updated optimization engines, and an analysis backbone based on the industry's golden sign-off tools.
Xpedition updated for schematic verification and DFT
Mentor's flagship PCB suite is aiming to offer another 'shift left' in verification as respins rise.
Case study: Achieving earlier signoff convergence and a ‘shift left’ for P&R at Qualcomm
Qualcomm has described its use of Calibre RealTime Digital to enhance its P&R flow.
Accellera updates UVM reference implementation
Accellera has updated the reference implementation for the Universal Verification Methodology to reflect the changes made for the latest release of the standard.