Design Compiler updated for 5nm and beyond

By Luke Collins |  No Comments  |  Posted: November 30, 2018
Topics/Categories: Blog - EDA  |  Tags: ,  | Organizations:

Synopsys has updated Design Compiler, the IC industry’s RTL synthesis workhorse, to add optimization techniques that speed up its operation and make it suitable for use on designs at process nodes of 5nm and beyond.

Design Compiler NXT gains power-driven mapping and structuring techniques, concurrent clock and data (CCD) optimization, and an updated approach to distributed synthesis that does not sacrifice quality-of-results.

The tool also shares libraries and advanced placement technologies with IC Compiler II, in addition to aligned RC, net topology, and density modelling, to enable tighter correlation between the two tools and hence better end results.

Synopsys claims tool runtimes can be half those of Design Compiler Graphical, thanks to improvements to the core code of the tool and a new approach to multi-threading that improves scalability up to eight cores. There is also an updated approach to distributed processing: an intelligent partitioner breaks the workload down into smaller jobs and then sends them off to multiple machines for optimization, but ensures each operates with the full physical and logical context of the design.

Synopsys also claims that Design Compiler NXT can save up to 5% of dynamic power consumption without degrading timing, area or congestion metrics, by using new techniques for mapping, restructuring, and rewiring. Techniques borrowed from IC Compiler II for concurrent clock and data optimization improve timing and power recovery through dynamic skew management.

Advanced process nodes have their own design challenges and Design Compiler NXT has features that address these physical issues, including support for creating via pillars, ‘pattern must join’ instances, automatic use of non-default rules, pin-access awareness, variant- aware libraries, layer-aware optimization, and other requirements.

These features enable closer correlations between RTL synthesis outputs and layout results. This is why Design Compiler NXT has been updated to align the way it undertakes tasks such as estimations of net topology parasitics with the way that IC Compiler does them. Correlation between synthesis and place-and-route is further improved by using high-accuracy timing models for path-by-path and endpoint-by-endpoint calculations.

Design Compiler NXT also share libraries and block abstract models with IC Compiler II, so that the same libraries can be used for synthesis and place-and-route. This helps avoid the synthesis, place-and-route, and physically-aware signoff-driven ECO processes using different models, in situations in which models are evolving throughout the design process.

There’s more on Design Compiler NXT from Michael Jackson, corporate vice president, marketing and business development, Synopsys, here; from Sassine Ghazi, co-general manager, design group, Synopsys, here, and Abhijeet Chakraborty, group director, R&D, design group, Synopsys, here. You can get a datasheet on Design Compiler NXT here.

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