Synopsys fuses synthesis and place-and-route to improve IC design quality and time to results

By Luke Collins |  No Comments  |  Posted: November 27, 2018
Topics/Categories: Blog - EDA, - Product  |  Tags: , ,

Synopsys has released Fusion Compiler, an RTL-to-GDSII tool that combines the synthesis and place and route tasks. The tool has been in trials with customers since earlier in the year, and has already been used to tape-out advanced IC designs by some of them.

Fusion Compiler uses a single, scalable data model, updated optimization engines, and an analysis backbone based on the industry’s golden signoff tools. Synopsys says that this approach can lead to up to 20% better results, achieved up to twice as fast, as with previous-generation tools.

Fusion Compiler’s data model contains both logical and physical information, and has been architected to support ultra-large designs of hundreds of millions of instances in the smallest possible memory footprint.

The use of a common data model enables sign-off analysis, optimization, concurrent clock and data optimization, clock topology creation, and routing engines to work together to optimize a design in a predictable way.

The data model also makes it possible to share technologies across the RTL-to-GDSII design flow, for example between synthesis and place and route, to achieve the best balance of timing, power, and area for the application.

Fusion Compiler should also enable faster design, by blurring the boundaries between synthesis and physical implementation with a unified physical synthesis optimization flow that reduces the need for iterating between the RTL development and place-and-route processes. The use of signoff-quality engines throughout the tool reduces the need for excessive design margins, and should also reduce the number of late-stage convergence issues.

To improve overall performance, Synopsys is applying distributed processing strategies, parallelization, and multi-threading to key engines within the tool. Synopsys says that other techniques, such as interleaved floorplanning and synthesis, physically-aware data-path representation, logic re-synthesis during physical implementation, and a unified approach to physical synthesis optimization, can together deliver results that are up to 20% better than previous approaches.

Unified physical synthesis (UPS) supports features such as layer-aware optimization, macro skewing, advanced 2D legalizers, route-driven estimation for modelling congestion, and concurrent clock and data optimization. It also handles multi-bit banking and de-banking, power-optimization strategies that focus on reducing total power consumption, automatic application of non-default rules, and via-ladder support for advanced nodes.

Fusion Compiler has been designed for use on the most challenging process nodes, and so provides support for multi-patterning lithography and the use of finFETs. During synthesis, the advanced legalizer in UPS handles inbound cells, regular standard cells and multi-bit registers, while making trade-offs to meet timing and area constraints. The placement engine is engineered to support the fin grid, spacing rules for implants, continuous diffusion, variable-threshold cell spacing rules, and cross-row rules to minimize multi-patterning violations. The routing engine supports complex routing rules including cut-metal aware routing, preferred grid extension, via pillars, and intelligent multi-patterning avoidance and repair.

To find out more about Fusion Compiler, Synopsys has created a series of video by some of the people most deeply involved in its development.

Sassine Ghazi, co-general manager of the design group at Synopsys, uses his video to explain how Synopsys is evolving its digital design toolset, and to position the introduction of Fusion Compiler versus the simultaneously announced Design Compiler NXT.

Shankar Krishnamoorthy, senior vice president engineering, design group, Synopsys, describes how Fusion Compiler brings together synthesis, place and route, analysis and sign-off tools within a single data model.

Reiner Genevrieve, vice president engineering, design group, Synopsys, uses his video to describe the way in which the use of a common data model has enabled the creation of a single design cockpit and reduced iterations between the RTL development process and physical implementation.

Aiqun Cao, group director, R&D, Synopsys, uses his video to talk about the implementation of ‘unified physical synthesis’ to provide the ‘nerve centre’ and backbone of Fusion Compiler’s capabilities.

Finally, Neeraj Kaul, vice president engineering, design group, Synopsys, discusses the advantages of embedding sign-off quality RC extraction and timing-analysis engines within Fusion Compiler.

There’s also a datasheet here.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors