Arm is pushing more work onto Arm servers in the AWS cloud as it encourages EDA vendors to port their tools to the architecture.
Study may point to new challenges in more bidirectional AMS implementations on SoC-class designs, though formal and emulation help keep respin count in check.
Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)
Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.
Use of the open-source RISC-V processor was tracked for the first time by the biennial study, finding notably high take-up.
A partnership between Siemens and VSI, a real-world autonomous vehicle research company, aims to refine and promote digital twin strategies.
Among the papers that will be presented at the end of October, this year's DVCon Europe will demonstrate the benefits of taking good ideas from wherever you can in the pursuit of more effective verification flows.
Increasing complexity means that teams must leverage automation to work across disciplines, speed delivery and free room for innovation.
DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.
Talks in the Design-on-Cloud Pavilion at this year’s DAC demonstrated how the question over its usage is not so much whether design could or should migrate to the cloud but how to optimize cost and performance when it’s there.
The combination of Embedded Linux and Azure is supported by services and technologies that speed the delivery and deployment of MCU-based projects.
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