Mentor Graphics

Embedded hardware and software are experiencing exciting advances but free, open source technologies only go so far in connecting them. Help is on the way.

You can now get a complete system-level flow, but bundling 'free' ESL with RTL tools slows the methodology shift, says the leading design analyst. Meanwhile, Cadence moves into the number two vendor slot, but the battle rages on.

The Mentor chief discusses ESL-based low power, emulation, 32nm to 20nm and using tools in the cloud.

Mentor Graphics has added to its HyperLynx suite a tool that uses design-rule check (DRC) techniques rather than simulation to look for potential signal-integrity problems.

New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.

IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology

With the foundry giant set to take the wraps off its latest flows and innovations in just seven days, remember that you must pre-register to attend its Silicon Valley event. Also here are some pre-event pointers.

The EDA giant fills out its prototyping and verification line-up with a long-mooted acquisition, and is set to become the first of the 'big three' to offer an in-house soup-to-nuts flow.

Accellera has approved version 1.0 of the Unified Coverage Interoperability Standard (UCIS). Here's how it works.

Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.