Mentor’s Valor tightens PCB design-to-manufacture links
Valor NPI-based flow claims first in automating the passage of drawings to fabrication, and enabling dynamic DFM feedback from manufacturers.
Mentor Graphics
Mentor buys BDA for AMS portfolio
Mentor Graphics has bought Berkeley Design Automation (BDA), a specialist in analog, mixed-signal, and RF circuit verification using FastSpice.
Mentor begins to take wraps off Xpedition PCB software overhaul
New-look Xpedition flow launches with preview of layout features including better control over automation, 2D/3D views, and a UI even for 'casual' users.
Cadence to buy Forte and build out HLS offering
EDA giant cites high-level synthesis' move into the mainstream as driven by IP integration challenges in striking deal for the HLS market leader.
Complexity to force shift to four-stage verification
The complexity of on-chip interconnect and the relentless growth in software size will drive the move to a four-stage verification process as well as the increased use of formal techniques to speed up SoC-level testing, Mentor Graphics verification specialist Mark Olen claimed at the Verification Futures conference.
Mentor targets PCB ERP ‘missing link’
Valor additions aim to deliver shopfloor data to PCB ERP systems in real time... for the first time. And could boost ROI beyond 70%.
Latest Nucleus RTOS offers secure memory partitioning for mid-market design
Mentor's new version of its RTOS targets once high-cost flexibility with secure and reliable in-operation upgrades and app swap-outs for medical, industrial and smart energy.
Verification Futures rolls out in Europe next month
The one-day conference series features the latest innovations from many verification vendors in separate UK, France and Germany editions.
SoC design gets hierarchical test strategy, improved compression; system design gains end-to-end IJTAG integration strategy
Synopsys automates standards-based hierarchical test insertion and improves test compression for SoCs; Mentor teams with ScanWorks for system-wide IJTAG.
UPF group moves to consider system-power issues
The group that developed the IEEE 1801 Unified Power Format standard is looking to bringing power modeling and estimation to the system level for version 3.0, due in 2015.