EDA

Variable lifetimes are an apparently basic but also tricky feature within the verification language.

Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.

The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.

A new white paper offers useful tips and techniques for PDN analysis and performance optimization in designs such as those using DDR4.

A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.

Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.

Learn how to ingest data from multiple engineering teams in multiple formats on interposer and other multi-dimensional projects.

System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.

Silicon Photonics 3D integration posed LVS challenges in this fast emerging technical space. A case study describes how the two institutions overcame them.

Advanced packaging requirements from foundries and OSATs pose stringent challenges. A new paper describes three ways of satisfying them.