Blue Pearl Software will use DAC to announce closer integration between its tools and Xilinx’s Vivado Design Suite, as well as new methodologies for working with ARM cores.
Earlier this year, the company announced release 6.0 of its Software Suite and stronger links to Synopsys’s Synplify Pro tool.
The Blue Pearl tools focus on improving the quality of results generated by FPGA synthesis by analysing the RTL of the design and developing timing constraints in SDC format that can be passed through to place and route.
According to Shakeel Jeeawoody, vice president of marketing at Blue Pearl Software, many of the issues that have already been experienced in ASIC design are now affecting FPGA designs.
“Customers are telling us that it is taking 15 hours to do one pass [through the FPGA design tools], they’re not closing timing and its taking 40 to 45 turns to get to timing closure,” he said. “If you just keep running synthesis and place and route, it is not enough to get the job done.”
Other parts of the Blue Pearl toolset can compare the constraints its creates with SDC decks produced manually.
“We believe our SDC is exhaustive so we will show everything that is common, everything we have generated and you did not find, and things that you found that we don’t think are important,” said Jeeawoody.
On the ARM front, Blue Pearl is developing a ‘grey box’ methodology that will enable it bring the kind of RTL analysis and constraints generation to designs including the ;company processor cores.
Jeeawoody says that the problem with integrating blocks of IP such as ARM cores into larger designs is that doing so can create issues between IP blocks, or with signals that cross clock domains.
“If you have full RTL models it is perfect but the simulation takes forever,” he said. Using black-box models tells you what signals go in and out of the block, but not much more.
“With grey-box models you expose a single level of logic up to a register to enable inter-block analysis. Having that information will reduce field failures.”