The drive to ease time-consuming partitioning in FPGA prototyping – and the competition – is hotting up. Indeed, FPGA will be one of the bigger focus areas at this year’s Design Automation Conference. Synopsys recently upgraded its Synplify Pro software, Xilinx has launched its Vivado Design Environment, and Blue Pearl Software is also boarding the Vivado bus, having recently extended its hooks into Synplify.
If those established players are on your agenda, you might also want to check out French start-up Flexras Technologies (Booth #2810), which is attending the Design Automation Conference for the first time. The company has been in stealth mode since 2009 and will be taking the wraps off its Wasga Compiler, which it claims to be the “first timing-driven, multi-FPGA partitioning software” for both Xilinx and Altera boards (the company also has already struck an alliance with Xilinx, alongside one with board supplier The Dini Group).
The bottom line on all this is a claimed 10X improvement in performance for multi-billion gate designs. That’s mighty fine talk.
We’re hoping to sit down with Hayder Mirabet, CEO, to follow up on the technology and the claims for it at the show, but before then a few other details on Flexras caught our eye.
The company is out of the University of Pierre and Marie Curie and France’s highly respected LIP6 Lab. Both institutions frequently crop up with some of the more innovative papers at Europe’s DATE conference, so Flexras has the right kind of pedigree. It’s also had French government backing and is a lead player in PPR, the EU-backed project addressing rapid prototyping technologies.
Flexras’ technology has also caught the eye of DAC’s conference organizers, and it is co-presenting a poster describing the Wasga Compiler’s use with Xilinx as part of DAC’s User Track (Wednesday, June 6, 12.30-13.30).
As a further taster, here’s how Flexras describes the main features of its technology on its website.
Smart design hierarchy management with selective preservation of hierarchical blocks:
- Considerably reduces partitioning complexity
- Keeps the global netlist view during the partitioning process
Multiple clock domain management
- Each clock-domain paths is optimized independently
- Critical paths crossing the FPGA are reduced
- The multiplexing ratio is reduced when crossing signals exceed FPGA pins
- Critical signals with low slacks are not multiplexed
Through FPGA routing
- Overcrowded board traces are avoided to reduce the multiplexing ratio
Timing graph back annotation (based on FPGA timing tools)
- Provides accurate internal FPGA delays estimation
Timing budgeting for FPGA PnR
- To meet prototyping system clock frequency
Optimized synchronous inter-chips communication IPs (SERDES/LVDS)
- Reduce wire sharing delay to achieve high system performance