DAC 2012: Synopsys marries virtual and FPGA prototyping

By Paul Dempsey |  1 Comment  |  Posted: June 7, 2012
Topics/Categories: Blog Topics, Commentary, ESL/SystemC, Verification  |  Tags: , , ,  | Organizations:

A typical project today is a mixture of new functionality and innovation and more mature RTL. Innovation within prototyping flows has recently looked at how to link these partitions to allow engineers to advance each area as quickly as possible.

Synopsys has now unveiled an interesting approach that can directly link system-level, virtual sections of a design to stable code that is already capable of being ported to an FPGA.

The new Hybrid Prototyping Solution takes the company’s Virtualizer¬†virtual prototype software to its HAPS FPGA boards, and while the concept is easy enough, it’s obviously been tricky to implement.

So, for the newer elements of the design, you generate a model-based virtual version and then connect that directly to a HAPS board hosting mature re-used RTL.

This is not a fully-fledged FPGA prototype in the traditional sense. Rather, the idea is that you have a more mature, early-stage platform in which to catch potential hardware and software issues before you go into what can be a lengthy RTL simulation. It’s an intriguing way of exposing a virtual concept to real-world conditions early on.

However, once you take that virtual vision into hard, simulated RTL the full FPGA prototype remains at the end of the flow. The hybrid is, then, a pretty clever upsell for Synopsys: more HAPS boards and more reassurance about the virtual protoyping concept as it now can offer a real-world gateway.

And if it can pay for itself by shaving another big notch off simulation and emulation times, what’s the cause for complaint?

Not that surprisingly, the new product has a strong ARM flavor, with access to Cortex  models and AMBA interconnect transactors.

The hybrid was shown at DAC and is now available to early adopters.

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