DAC 2012: Atrenta to automate production of power-intent constraints

By Luke Collins |  No Comments  |  Posted: May 29, 2012
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Atrenta is working on an architectural-level power-planning tool that will automatically generate power-intent constraints in UPF (Guide) or CPF format.

The unannounced product is meant to help designers define the different power and voltage domains of their chips at the architectural level, and will then generate constraints expressing this intent that can be passed forward to the RTL stage and beyond.

The product will be based on aspects of Atrenta’s Gensys SoC assembly tool and its evolving SpyGlass power-analysis and constants-management tools.

“There are consultants out there who are being paid to write UPF,” said Kiran Vittal, senior product marketing director at Atrenta. “Customers tell us they want an automated way of doing this.”

At DAC, Atrenta will be emphasising three enhancements to its Spyglass Power tool, developed as response to widening uptake of power-aware design, including from the networking and server markets.

The first involves exposing more of the intermediate results created during a power analysis run to improve the accuracy of power estimation in ASIC design flows. ASIC vendors give customers spreadsheets to populate with data such as the number of blocks, the number of registers and signal activity in their designs, as a basis for power estimations. The accuracy of the activity data has a large influence on the estimate’s reliability, but according to Vittal, can lead to wildly inappropriate estimates.

Cisco, a customer, found that its ASIC vendor was providing power consumption estimates that were 50 to 100% too high. (Cisco personnel will be discussing this at User Track presentation 2U.6 on Tuesday). It asked Atrenta to expose more of the intermediate data that its power analyse tool generates, so that it could have a more accurate idea of things like the amount of power used by each clock domain, the balance of power use between sequential and combinatorial logic, and the details of memory read and writes.

“We had all this information in the tool but we weren’t spitting it out,” said Vittal, “so now we are spitting it out to put into the spreadsheet. Ultimately, the power numbers we spit out are within 15 to 20% of the real silicon consumption.”

The second enhancement to SpyGlass Power involves improving the way that the tool can optimise clock gating to reduce power. One strategy is to do a formal analysis of memory control logic to reduce redundant Reads and Writes. Another looks at shutting down memory blocks on an almost cycle by cycle basis, so that if you know that a memory value will not be needed until cycle five of seven it can be powered down in the meantime.

Vittal says that there are two ways in which the tool can be used. In the first, it generates a list of power-saving opportunities, listed by most effective first, for the designer to choose from. Once the logic has been updated to implement the chosen opportunities, eh designer can then simulate the logic again to verify its function.

In the second approach, which might be used when the RTL has been generated from a high-level synthesis tool, the Atrenta tool can update the RTL. A sequential formal analysis then shows that the ‘before’ and ‘after code is functionally equivalent.

The third enhancement to the Spyglass Power tool is support for the new language constructs in UPF 2.0, which is used by designers to define power and voltage domains.

“In UPF 1.0 you might have to define a power intent in 20 lines,” said Vittal. “In UPF 2.0 you can capture it in one line.”

Atrenta is on booth #2230 at DAC.

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