DVCon US 2020 preview: Mentor

By TDF Editor | No Comments | Posted: February 24, 2020
Topics/Categories: Blog - EDA, - HLS, Next Generation Design, Standards, Verification | Tags: | Organizations: DVCon, Siemens EDA

STOP PRESS: Please note that DVCon US has been shorted by a day because of the COVID-19 outbreak and will now end on Wednesday, March 4. An updated conference program is available here. Please use it to confirm whether events you plan to join have been moved or cancelled. Delelgates should also visit the DVCon US for details on healthcare protocols they are asked to follow.

DVCon US begins next week at its usual venue, the Double Tree Hotel in San Jose, running March 2-4 (Exhibition March 2-4). Mentor, a Siemens business, will provide a range of expert advice and presentations across the conference program and at its stand (Booth 404).

Its team will be on hand to discuss the latest developments in areas such as Portable Stimulus, UVM, formal verification, clock domain crossing, low- power verification, high-level synthesis and more.

A full list of Mentor’s activities can be found here, but you should also confirm timings at the DVCon website. What follows is a list of some of its main events.

Please confirm the times of all events below at the links below and the DVCon website, where an updated technical program is available. See above.

Featured tutorial

Application Optimized HW/SW Design & Verification of a Machine Learning SoC
Thursday, March 5, 8:30am – 11:30am, Donner

This tutorial will walk attendees through the process of migrating an algorithm from generic software to a hardware implementation customized to the specific requirements of a system. It will help you to make intelligent trade-offs between hardware and software along the way and explain the tools and techniques needed to go from ‘Software to Systems’. To reach these goals, it will cover a broad range of techniques including simulation, emulation, prototyping, and high-level synthesis so that you can design and verify both SoCs and the software that runs on them.

Featured panel

Predicting the Verification Flow of the Future
Wednesday, March 4, 1:30pm – 2:30pm, Oak/Fir

Moderator Jean-Marie Brunet from Mentor, a Siemens Business, will lead a panel of verification experts on an exploration of what the future verification environment will look like. They will attempt to predict the longevity of simulation and formal verification, and determine how far emulation can be extended across the verification flow. The role of standards will be addressed, as will the issue of when analog will have a place in digital functional verification.

Short workshops

How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity
Monday, March 2, 3:30pm – 5:00pm, Oak

Mind the GAP(s): Closing and Creating GAPS between Design and Verification
Thursday, March 5, 1:00pm – 2:30pm, Siskiyou

Technical papers

Designing PSS Environment Integration for Maximum Reuse
Tuesday, March 3, 9:00am – 10:30am, Fir

UVM – Stop Hitting Your Brother Coding Guidelines
Tuesday, March 3, 3:00pm – 5:00pm, Oak

Multi-Level Replay of VIP Models in Isolation from Original Design Verification Environment to Enhance Protocol Analysis and Debug
Tuesday, March 3, 3:00pm – 5:00pm, Fir

UPF 1.0, UPF 2.0, UPF 2.1, UPF 3.0, and Now UPF 3.1: The Big Q: ‘Which is the Right Standard for My Design?’
Tuesday, March 3, 3:00pm – 5:00pm, Monterey/Carmel

Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock Domain Crossing Verification
Tuesday, March 3, 3:00pm – 5:00pm, Monterey/Carmel

Systematic Methodology to Solve Reset Challenges in Automotive SoCs
Wednesday, March 4, 3:00pm – 4:30pm, Monterey/Carmel

Scalable Reset Domain Crossing Verification Using Hierarchical Data Model
Wednesday, March 4, 3:00pm – 4:30pm, Monterey/Carmel

SystemVerilog Constraints: Appreciating What You Forgot in Class to Get Better Results
Wednesday, March 4, 3:00pm – 4:30pm, Oak

Poster session

Tuesday, March 3, 10:30am – 12:00am, Gateway Foyer

4.3 – Covergate: Coverage Exposed

4.8 – How UPF 3.1 Reduces the Complexities of Reusing Power Aware Macros

4.11 – Are You Safe Yet? Safety Mechanism Insertion and Validation

4.14 – Deadlock Verification for Dummies – The Easy Way Using SVA and Formal

Exhibition

Mentor (Booth #404) will host daily theater sessions and running demonstrations across the full range of its latest Enterprise Verification Platform.

Specific tool families in the spotlight will include Catapult High-Level Synthesis for C-level verification and PowerPro for power analysis; Questa for simulation, low-power, VIP, CDC, formal and support for UVM and Portable Stimulus; and Veloce for hardware emulation and system of systems verification, unified with the Visualizer debug environment.