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Ferroelectric memory may be able to stage a comeback thanks to materials innovations as work presented at VLSI Symposium have shown, though there is still plenty to do.

The Joules RTL Design Studio aims to make coding more aware of aware of physical issues before and after hand-off for implementation.

Western Digital's head of technology set out at the recent VLSI Symposium the ways in which flash makers can scale without costs accelerating.

The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.

Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R

Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.

A UK cryogenic-CMOS research project has taped out its first demonstrator chip for core memory IP expected to be able to operate at close to absolute zero.

At the recent VLSI Symposium, Google vice president Parthasarathy Ranganathan described the importance of co-design and the software stack in its data-center designs.

The 69th annual IEEE IEDM has issued a call for papers seeking the world’s best original work in all areas of microelectronics research and development.

Single-device tracking in the chiplet and multi-chip age needs a boost to deliver accuracy and greater production efficiency.