Archives

DVCon Europe is looking for papers to be presented at this year’s event in mid-October.

Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.

Accellera has formed a working group to look at extensions to SystemVerilog to improve support for mixed-signal designs.

Cadence has introduced a platform for performing thermal and thermal-stress analysis of subsystems, from 2.5D and 3DICs to PCBs and complete electronic assemblies.

A new paper looks at examples for using The Boundary Condition Independent Reduced Order Model (BCI-ROM) in its VHDL-AMS implementation for electro-thermal analysis.

Workshops on portable stimulus, functional safety, verification of RISC-V processors, and design with chiplets and large language models will feature at the upcoming 2024 DVCon US.

At IEDM, CEA-Leti described a process that avoids the thermal problems of implementing CMOS transistors in the metal stack using monolithic integration.

Applied Materials and CEA-Leti have expanded their collaboration with the creation of a joint lab to develop materials useful for sensors, RF communications, and power devices, and with a focus on heterogeneous integration.

Start-up launches platform on path to the specification, emulation and simulation of large chiplet-based designs.

EMA Design Automation to launch sister company, Accelerated Designs, to help clients streamline processes, cut manual effort, and connect data.