Partitioning a verification test bench using native System Verilog transactors can make it easier to move between simulation and emulation.
Focus on systemic issues matches DVCon Europe event to European interests
Accellera has released the latest version of the Universal Verification Methodology (UVM) class reference document, with additions to the way in which testbenches can handle messages and registers.
VCS AMS updates AMS verification tool and methodology
Training company Doulos is working on a second version of its Easier UVM guidelines intended to speed up the process of getting a UVM testbench underway for new users.
Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL
Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.
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