UVM

June 25, 2014

Accellera releases version 1.2 of UVM

Accellera has released the latest version of the Universal Verification Methodology (UVM) class reference document, with additions to the way in which testbenches can handle messages and registers.
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March 26, 2014

Synopsys strengthens analog and mixed-signal verification with VCS AMS

VCS AMS updates AMS verification tool and methodology
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November 19, 2013

An easier start for UVM, take two

Training company Doulos is working on a second version of its Easier UVM guidelines intended to speed up the process of getting a UVM testbench underway for new users.
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March 16, 2012

DATE notebook: Aldec builds in more support for VHDL methodology

Aldec has updated its Riviera Pro tool to provide more support for OS-VVM, the recently launched verification methodology for VHDL
February 27, 2012

Synopsys verification IP launch has bite

Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.

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