Accellera Systems Initiative plans to kick off development of a set of extensions to UVM for mixed-signal design at a meeting in Munich, Germany next month (May 22).
The move follows a number of proposals presented at recent DVCon events that have addressed the need for analog and mixed-signal (AMS) extensions. Most of these proposals offer similar capabilities, but often use different implementations to resolve existing constraints enforced by UVM or to address limitations caused by mixing languages such as SystemVerilog and Verilog-AMS. The aim of the Proposed Working Group (PWG) is to explore how UVM mixed-signal extensions could be standardized.
“There have been many discussions in recent years about the need to make UVM more mixed-signal aware,” said Lu Dai, Accellera chair.
“Our ambition is to apply UVM for both digital and analog/mixed-signal verification,” added Martin Barnasconi, Accellera technical committee chair. “The UVM-AMS PWG will assess the benefits of creating analog and mixed-signal extensions to UVM and determine if a path to standardization is feasible. We encourage all interested companies to join our initial PWG meeting and provide input for standardization.”
The first meeting of the PWG will be held from 10am Wednesday, May 22 at NXP Semiconductors, Schatzbogen 7, 81829 Munich, Germany. The meeting will include presentations on industry best practices, discuss scope and requirements, and explore directions for standardization. Attendance is open to everyone, but registration is required.
Companies that have already shown an interest in standardization in this area include Xilinx, NXP Semiconductors, Infineon Technologies, Maxim Integrated, Ams, STMicroelectronics, Dialog Semiconductor, Cirrus Logic, and Renesas.