DVCon Europe looks to software for next phase in verification

By Chris Edwards |  No Comments  |  Posted: October 14, 2019
Topics/Categories: Blog - EDA, IP  |  Tags: , , , , ,  | Organizations:

The DVCon Europe conference, which takes place in Munich at the end of October, shows an increased focus on the role of software in electronic systems and the challenges it poses for verification, particularly for systems that need safety and security guarantees.

Joachim Geishauser, general chair and senior staff engineer at NXP Semiconductors, said the need in industries such as automotive to exploit greater levels of software programmability is driving changes in verification. “As process costs increase, you can’t provide specific hardware for each application. You don’t have enough parts to sell to justify the development costs. But hardware is providing more compute power, so the application-specific functions can be done in software.”

To maintain cost and energy efficiency, the hardware and software functions need to be more closely integrated, leading to the need for joint verification strategies. “It’s about enabling the hardware guys to see what the software guys have to deal with and other way round,” Geishauser said.

As part of the program, a tutorial from members of NXP will focus on the community about robotic drones and the relationship between hardware and software in those systems, said Ola Dahl, tutorial chair and a member of Ericsson’s ASIC development team. Another tutorial from Green Hills Software will focus on the software and hardware elements of simulation acceleration.

Another area that is gaining traction is machine learning. Geishauser said a panel will examine how machine learning can be applied to verification “and help release engineers from the tedious work of analyzing thousands of tests”. Other tutorials will look at techniques for building machine-learning systems and evaluating performance.

Similar to previous years, a strong theme of the conference is in UVM-based verification techniques. A number of papers will focus on safety and security aspects of verification in addition to mixed-signal testing using UVM.

DVCon Europe spans two days but a third day sees the return of the SystemC Evolution Day, a technical workshop on the system-level language. At DVCon itself, SystemC is the subject of verification-focused papers. According to Alexander Rath, technical program chair, and manager of functional verification at Infineon Technologies, notable papers cover parallel SystemC simulations and techniques for bringing SystemC together with Verilog and Python.

DVCon Europe starts on October 29, 2019.

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors